139 lines
4.9 KiB
C
139 lines
4.9 KiB
C
/* KallistiOS ##version##
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aica_cmd_iface.h
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(c)2000-2002 Dan Potter
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Definitions for the SH-4/AICA interface. This file is meant to be
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included from both the ARM and SH-4 sides of the fence.
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*/
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#ifndef __ARM_AICA_CMD_IFACE_H
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#define __ARM_AICA_CMD_IFACE_H
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/* $Id: aica_cmd_iface.h,v 1.3 2002/06/13 05:52:35 bardtx Exp $ */
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#ifndef __ARCH_TYPES_H
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typedef unsigned long uint8;
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typedef unsigned long uint32;
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#endif
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/* Command queue; one of these for passing data from the SH-4 to the
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AICA, and another for the other direction. If a command is written
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to the queue and it is longer than the amount of space between the
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head point and the queue size, the command will wrap around to
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the beginning (i.e., queue commands _can_ be split up). */
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typedef struct aica_queue {
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uint32 head; /* Insertion point offset (in bytes) */
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uint32 tail; /* Removal point offset (in bytes) */
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uint32 size; /* Queue size (in bytes) */
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uint32 valid; /* 1 if the queue structs are valid */
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uint32 process_ok; /* 1 if it's ok to process the data */
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uint32 data; /* Pointer to queue data buffer */
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} aica_queue_t;
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/* Command queue struct for commanding the AICA from the SH-4 */
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typedef struct aica_cmd {
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uint32 size; /* Command data size in dwords */
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uint32 cmd; /* Command ID */
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uint32 timestamp; /* When to execute the command (0 == now) */
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uint32 cmd_id; /* Command ID, for cmd/response pairs, or channel id */
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uint32 misc[4]; /* Misc Parameters / Padding */
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uint8 cmd_data[0]; /* Command data */
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} aica_cmd_t;
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/* Maximum command size -- 256 dwords */
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#define AICA_CMD_MAX_SIZE 256
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/* This is the cmd_data for AICA_CMD_CHAN. Make this 16 dwords long
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for two aica bus queues. */
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typedef struct aica_channel {
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uint32 cmd; /* Command ID */
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uint32 base; /* Sample base in RAM */
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uint32 type; /* (8/16bit/ADPCM) */
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uint32 length; /* Sample length */
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uint32 loop; /* Sample looping */
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uint32 loopstart; /* Sample loop start */
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uint32 loopend; /* Sample loop end */
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uint32 freq; /* Frequency */
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uint32 vol; /* Volume 0-255 */
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uint32 pan; /* Pan 0-255 */
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uint32 pos; /* Sample playback pos */
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uint32 pad[5]; /* Padding */
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} aica_channel_t;
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/* Declare an aica_cmd_t big enough to hold an aica_channel_t
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using temp name T, aica_cmd_t name CMDR, and aica_channel_t name CHANR */
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#define AICA_CMDSTR_CHANNEL(T, CMDR, CHANR) \
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uint8 T[sizeof(aica_cmd_t) + sizeof(aica_channel_t)]; \
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aica_cmd_t * CMDR = (aica_cmd_t *)T; \
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aica_channel_t * CHANR = (aica_channel_t *)(CMDR->cmd_data);
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#define AICA_CMDSTR_CHANNEL_SIZE ((sizeof(aica_cmd_t) + sizeof(aica_channel_t))/4)
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/* Command values (for aica_cmd_t) */
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#define AICA_CMD_NONE 0x00000000 /* No command (dummy packet) */
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#define AICA_CMD_PING 0x00000001 /* Check for signs of life */
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#define AICA_CMD_CHAN 0x00000002 /* Perform a wavetable action */
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#define AICA_CMD_SYNC_CLOCK 0x00000003 /* Reset the millisecond clock */
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/* Response values (for aica_cmd_t) */
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#define AICA_RESP_NONE 0x00000000
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#define AICA_RESP_PONG 0x00000001 /* Response to CMD_PING */
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#define AICA_RESP_DBGPRINT 0x00000002 /* Entire payload is a null-terminated string */
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/* Command values (for aica_channel_t commands) */
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#define AICA_CH_CMD_MASK 0x0000000f
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#define AICA_CH_CMD_NONE 0x00000000
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#define AICA_CH_CMD_START 0x00000001
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#define AICA_CH_CMD_STOP 0x00000002
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#define AICA_CH_CMD_UPDATE 0x00000003
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/* Start values */
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#define AICA_CH_START_MASK 0x00300000
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#define AICA_CH_START_DELAY 0x00100000 /* Set params, but delay key-on */
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#define AICA_CH_START_SYNC 0x00200000 /* Set key-on for all selected channels */
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/* Update values */
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#define AICA_CH_UPDATE_MASK 0x000ff000
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#define AICA_CH_UPDATE_SET_FREQ 0x00001000 /* frequency */
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#define AICA_CH_UPDATE_SET_VOL 0x00002000 /* volume */
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#define AICA_CH_UPDATE_SET_PAN 0x00004000 /* panning */
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/* Sample types */
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#define AICA_SM_8BIT 1
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#define AICA_SM_16BIT 0
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#define AICA_SM_ADPCM 2
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/* This is where our SH-4/AICA comm variables go... */
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/* 0x000000 - 0x010000 are reserved for the program */
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/* Location of the SH-4 to AICA queue; commands from here will be
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periodically processed by the AICA and then removed from the queue. */
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#define AICA_MEM_CMD_QUEUE 0x010000 /* 32K */
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/* Location of the AICA to SH-4 queue; commands from here will be
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periodically processed by the SH-4 and then removed from the queue. */
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#define AICA_MEM_RESP_QUEUE 0x018000 /* 32K */
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/* This is the channel base, which holds status structs for all the
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channels. This is READ-ONLY from the SH-4 side. */
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#define AICA_MEM_CHANNELS 0x020000 /* 64 * 16*4 = 4K */
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/* The clock value (in milliseconds) */
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#define AICA_MEM_CLOCK 0x021000 /* 4 bytes */
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/* 0x021004 - 0x030000 are reserved for future expansion */
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/* Open ram for sample data */
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#define AICA_RAM_START 0x030000
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#define AICA_RAM_END 0x200000
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/* Quick access to the AICA channels */
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#define AICA_CHANNEL(x) (AICA_MEM_CHANNELS + (x) * sizeof(aica_channel_t))
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#endif /* __ARM_AICA_CMD_IFACE_H */
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